set_property PACKAGE_PIN Y18 [get_ports clk]
set_property PACKAGE_PIN M18 [get_ports dio]
set_property PACKAGE_PIN C2 [get_ports rclk]
set_property PACKAGE_PIN F4 [get_ports sclk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports dio]
set_property IOSTANDARD LVCMOS33 [get_ports rclk]
set_property IOSTANDARD LVCMOS33 [get_ports sclk]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_50M]

set_property BITSTREAM.GENERAL.COMPRESS true [current_design]